A NAND flash memory device, which is one example of a non-volatile semiconductor memory device, includes a page buffer circuit for performing various functions. For example, in reading data from memory cells of a selected page, the page buffer circuit senses data of the selected page and latches the sensed page data. In addition, when data are programmed in memory cells of the selected page, the page buffer circuit temporarily stores program data supplied from outside. The page buffer circuit is capable of preventing a program-inhibited cell or a program-completed cell from being programmed. Examples of the page buffer performing functions mentioned above are disclosed in U.S. Pat. No. 5,790,458 entitled “SENSE AMPLIFIER FOR NONVOLATILE SEMICONDUCTOR MEMORY DEVICE,” U.S. Pat. No. 5,761,132 entitled “INTEGRATED CIRCUIT MEMORY DEVICE WITH LATCH-FREE PAGE BUFFERS THEREIN FOR PREVENTING READ FAILURE” and U.S. Pat. No. 5,712,818 entitled “DATA LOADING CIRCUIT FOR PARTIAL PROGRAM OF NONVOLATILE SEMICONDUCTOR MEMORY”.
In performing a verification operation for confirming if programmed/erased cells have reached a target threshold voltage (if programmed/erased cells are sufficiently programmed/erased), the page buffer circuit, in the same way as a sensing operation, senses/latches data bits from memory cells of the selected page. To decide whether the latched data bits are pass data bits, the page buffer circuit provides the latched data bits to a program-status detecting circuit (also referred to as “a pass/fail check circuit”) without otherwise outputting the data from the page buffer. A NAND flash memory device having the program-status detecting circuit is disclosed in U.S. Pat. No. 5,299,162 entitled “SEMICONDUCTOR MEMORY DEVICE AND AN OPTIMIZING PROGRAMMING METHOD THEREOF.”
The program-status detecting circuit PS, which is disclosed in U.S. Pat. No. 5,299,162, includes pull-down transistors PD1–PD1024 connected to latches LT of page buffers PB, respectively. The pull-down transistors PD1–PD1024 are controlled by inversion outputs /Q of corresponding latches LT. Program/erase verification is carried out repeatedly until all pull-down transistors PD1–PD1024 are turned off.
After repeatedly performing the program/erase operation, a determination is made by the program status detection circuit whether all memory cells have been normally programmed/erased. Even after program/erase verification is carried out upon all effected memory cells, results of the pass/fail check circuit can indicate a program/erase failure. Such a program/erase failure may be generated, for example, by a defective memory cell. If the program/erase failure is caused by the defective memory cell, then the defective memory cell(s) is (are) substituted for redundant cell(s) in a known manner. After such substitution, a program/erase failure should not be indicated unless there was some additional cause of the failure.